size Design it
Here is what the circuit must do. Choose all the numbers, from nothing. This is the job a chip designer does by hand today, with a simulator open beside them.
Fales turns analog circuit design into a task a machine can grade. Five SPICE topologies, three kinds of task, every one generated backwards from a known working solution — so a solution provably exists and ngspice decides, in about 20 ms, whether an answer meets spec.
A circuit here is a fixed pattern of transistors, resistors and capacitors — the wiring is given and never changes. What is missing is the size of every part: how wide a transistor is, how large a capacitor is. Five to thirteen numbers depending on the circuit, and they all pull on each other. Widen one transistor and two requirements improve while a third quietly breaks.
So a task is a set of requirements, and an answer is one JSON object of numbers. A simulator then builds that circuit in software, measures it, and says pass or fail — the way a compiler either accepts your code or doesn't. Nobody reads the answer; nothing is a matter of opinion.
Here is what the circuit must do. Choose all the numbers, from nothing. This is the job a chip designer does by hand today, with a simulator open beside them.
Here is a finished circuit that misses its requirements. Exactly one value was changed to a wrong one. Everything looks plausible and the measurements are only slightly off — find which value, and fix it.
Here is a complete circuit with every value fixed. Say what it will do before anyone simulates it. No trial and error, nothing to search through — this one is purely about understanding the circuit.
| DC gain | how much it amplifies. 58 dB means about 800 times. |
| Unity-gain BW | how fast a signal can wiggle before it stops amplifying. 45 MHz means 45 million times a second. |
| Phase margin | how far it is from breaking into oscillation. Below about 45° a circuit rings; the tasks ask for 70°. |
| Total power | how much electricity it burns. 100 µW is a ten-thousandth of a watt. |
The other topologies measure different things — a voltage reference is graded on how little it drifts between −40 °C and +125 °C, a regulator on how well it rejects noise from its own supply, a comparator on how fast it flips. Same idea every time: a number a simulator can measure, and a requirement it either meets or does not.
Two baselines decide whether a model number means anything. The known solution must score 100% — otherwise the tasks are broken. Random search must score a few percent — otherwise they are trivial.
Sample a valid design, simulate it, relax the measured result slightly and call that the requirement. The answer exists before the question does.
Every candidate task is attacked by random search before it is allowed in, and discarded if random search cracks it.
Legality is checked before simulation: ranges, types, missing and invented keys. Six known attacks on it are in the test suite and all must stay blocked.
Each spec scores 0–1 by how far off it is, +0.5 only when every spec passes. Binary pass/fail gives a model no gradient to learn from.
Honest limits: textbook LEVEL=1 device models, five fixed topologies, no process corners. The verifier is exact and identical for everyone, which is all the gap measurement needs.